1. Field of the Invention
The present invention relates testing algorithms and methods for optimizing functionality, while reducing a chip's physical pad and/or pin count.
2. Description of the Related Art
Testing circuitry is a critical function that must be performed to confirm whether a circuit design functions as intended. A common type of testing is performed using logic and methods defined by some or all of the IEEE 1149.1 Test Access Port and Boundary-Scan Architecture, which is herein incorporated by reference. One type of scan testing is referred to as “boundary scan” testing, that allows complete controllability and observability of the boundary pins of a Joint Test Access Group (JTAG) compatible device via software control. Another type uses scan chains to test the combinational logic of a design. Scan chain testing is a common technique used in Design for Test (DFT). DFT techniques add certain testability features to a hardware product design. In scan testing, the added features are special flip flops, called “scan flops”. A signal called scan enable is used to assert the scan-flops in the design, to define a long shift register, where input pins called scan-in provide the data to the chain, and output pins called scan-out connect to the output of the chains. When the chip is placed in scan mode, a test pattern can be entered into the chain of scan-flops, provided to the chip's combinational logic being tested, captured, and then read out from the scan-out pins. The output can then be compared to expected results to determine faults in the design. Once scan mode has commenced, the testing will continue until complete, unless a reset is triggered. The chip can exit scan mode upon completing testing, as long as the test mode register can be modified to different values other than scan mode. Nevertheless, a reset may be mandatory when the chip is in a chaotic state.
As noted, certain pins are required to be added to a chip design, which provide access to the testing logic embedded in the chip. Among the known pins required to enable testing, communicate test patters, and output testing pattern results, it is also common to include a test reset pin. Another DFT reset may be required to reset the scan flip flops for certain ATPG algorithms; which will not reset test mode registers and is different from a test mode reset. Normally another dedicated pin is used for that purpose. During a testing process, however, the test engineer or test software may determine that it is time to stop the testing. To do so, the test reset pin is used to communicate reset to test mode registers of the test controller. If the test reset pin is eliminated, without maintaining a reset functionality, the chip must be powered down. A power-down and power-up cycle is time consuming, and would take up precious tester time, which becomes even worse when delay-related tests become mandatory for controllers using nanometer and smaller node technologies.
Further, as more logic and functionality continues to be added to specialty chips and processors, so does the need for more chip pads and package pins. Consequently, although the size of chips and the density of logic manufactured into chips continues to increase, the physical need to interface with the chip continues to force designers to increase a chip's pad area and package size simply to add pins. Although some pads/pins are required to enable chip functionality, others, such as test related pads/pins, serve limited usefulness.
It is in this context that embodiments of the present invention arise.